Barracuda PreSilicon Emulation

Fig. 2 pin layout FPGA #1

output core_secure_t2;

output core_mdrste;

inout core_bkgd;

output core_wakeup_ta;

input peri_test_clk;

input peri_test_clk_enable;

input peri_cop_failure_vector;

input peri_monitor_failure_vector;

input peri_pllsel_t3;

input reset_pin_input_b;

input test_mode_en;

input romon_exp_state;

input reg_sw0;

input pag_sw1;

input pag_sw0;

input ram_sw2;

input ram_sw1;

input ram_sw0;

input rom_sw1;

input rom_sw0;

input eep_sw1;

input eep_sw0;

input fee_hold_t1;

input ee_hold_t1;

input secure;

input peri_cwai_t3;

input peri_syswai_t3;

input peri_rtifff0i_t3;

input [GIBW-1:0] peri_ffxx_t3;