Logic simulation is indispensable for the verification of digital design systems. However, due to the high computational complexity of the problem, logic simulation by software cannot verify the behavior of large digital systems. Logic emulation systems using single or multiple FPGA's are capable of emulating complex digital system designs several orders of magnitude faster than software simulators. As a result, FPGA-based logic emulators can verify large designs that otherwise are not verifiable by software simulators. [12]
For logic emulation, the author has first mapped the design to FPGA's and partitioned the design into parts, each of which can fit inside a single FPGA on the logic emulator. The computer-aided design tool Max II+ developed for ALTERA FPGA's has then be used to complete the internal design of each individual FPGA. Finally, the author has performed board-level routing to connect the signals between the FPGA chips.
The Barracuda logic emulator consists of FPGA chips, interconnected by a set of multiterminal nets on the circuit board. In this thesis, the author addresses the problem of board-level routing applicable to the Barracuda logic emulator system that has been developed.
Motorola is developing a new generation of MCU's for automotive
applications. Since these devices are used e.g. for airbag controls within
cars, an error free design has to be guarantied. This requires a higher level
of design verification.
Another basic motivation is to provide customers a working platform that has
basically the same functionality and timing as the chip to be developed. The
emulator can be used to develop and test software dedicated to the Barracuda
MCU before the chip is shipping.
The first issue of this thesis is to study and evaluate the Barracuda
modules. This is necessary to identify not synthesizable modules in RTL code
and substitute this analogue modules and hardmacros to prepare the complete
Barracuda design for FPGA implementation.
The second main issue is to develop an IPbus interface for each interface
module to allow modules to be put together to provide basic information e.g.
size, pincount, package and number of FPGA's. Then we try to select FPGA's that
meet best the requirements for speed and functionality, necessary for the
prototype board. The term try as used here, especially means to chose correct
pin count and estimate the correct number of necessary logic elements of each
FPGA, as at time of this thesis, the modules weren't complete and the pincount
as well as the size of the modules were subject to change.
The third main issue of the thesis objective is interpreted to be: Establish
and extend the functionality of a generic solution to automatic creation of
schematics and board layout using FPGA pin information from some output files
created by FPGA P&R tool. This guarantees an error free design
Through the work with the thesis it has become evident the third main issue
will precede. First, the Barracuda design has been implemented to FPGA, next
the effects of different strategies for board-level design are studied and
evaluated in this context.
Figure 1.1: The Structure of the Thesis.
The process of mapping logic onto the multi-FPGA prototype board and developing the board went through the following stanges. First, after substituting all not synthesizable modules in the design at RTL-level, the logic has been converted into functions that fit the logic blocks in the FPGA's using logic synthesis and technology mapping. Second, the Barracuda design has been partitioned to different FPGA's using wrapper modules. Third, the inter-FPGA signals have been routed globally and optimized using pin assignments. Forth, the schematics and layout of the board have been developed using an automatic PCB design system, developed in the course of this thesis, to translate the hardware specifications into script files for the schematic capture and P&R tool Eagle to automatically create schematics and board layout.
The PCB design tool that automatizes PCB design has been developed additionally to the initial objective of this thesis because of two mayor constraints. First, modules from old projects (the JUPITER project) had to be used for this work because the Barracuda project was in an early stage. These old modules had another bus-interface and size as well as pinout, that determine the board-architecture decisevely, were subject to change. Second, the schematics and layout of the multi-FPGA board that has a complexity similar to a Pentium board, is ready to be used immediately after the logic has been fitted into the FPGA's. The time to create schematics and board layout after design changes is reduced to minutes. It has been the aim, when designing the board, to find generic solutions and realizing them to provide a test-bed for different designing strategies. The focus has, in other words, been on developing a new approach that guaranties an error free design and allows design changes in minutes, redesigns and even new projects can be realized in days (former months) at board-level. Thus, the time to create a board is just as important as the resulting quality.
As can be seen from Figure 1.1, this thesis is divided into three chapters, one describing the work at RTL-level, one chapter describing the work on FPGA's and one chapter describing the work at board-level dealing with schematic capturing and PCB design automation using Perl. The majority of time has spent on preparing modules for FPGA emulation and the implementation of features that allow script based design entry at board-level as described in chapter 5. Due to time constraints, it was important to restrict the focus when designing the board. The focus has been put on completeness as well as on inventory values, particularly on developing generic design solutions. This is also reflected in the description of the developed PCB design tool in Chapter 5.
At begin of each chapter the theoretical background, an overview over the
used FPGA hardware and software tools is given.
First, the Barracuda project is introduced. The assumptions and motivation for
the thesis, outline the major contributions to the project, and provide a
general overview for the reader of the thesis.
Furthermore, chapter 2 describes our initial results on the subject of Barracuda PreSilicon Emulation at RTL-level. Because the focus of this thesis is on practical work, a brief overview of the Barracuda MCU is given. The chapter is not intended to provide a detailed overview on modern EDA tools and methods for digital circuits development using Field Programmable Gate Arrays (FPGA) but provides definitions, objectives, examples and the framework of this thesis. We present the problem of mapping a Verilog model, designed for a CMOS library, into a FPGA library, in the context of functionality and discuss several approaches to substituting analogue modules or hardmacros.
In
chapter 3 the reader is familiarized with
FPGA architecture, and FPGA design applications. The architectural tradeoffs on
the design of interconnection architectures using simple board-level routing
are investigated. The author then focuses specifically on design optimization
at FPGA-level applied to the Barracuda modules and ends with a review of the
work most relevant to this thesis--FPGA synthesis and pin layout.
In section 3.4 the assignment of
inter-FPGA signals to specific I/O pins on the FPGA's are described. It is
shown, that effective pin assignment reduces board-level routing expence
significantly.
Chapter 4 deals with the third factor of
the thesis, the barracuda prototype board.
In the following sections the hardware components of the prototype board are
listed and described. The chapter also presents opportunities for future
improvements, now focusing on integration and board layout. The last section is
directly based on the previous chapter, and gives a motivation for the use of
Design Automation to develop PCB boards.
Proceeding from the results in Chapter 4, Chapter 5 describes a novel approach for improving the
design process with the PCB design software Eagle by applying a novel design
tool. This chapter focuses on script-based design entry at board level and
describes the program interface of the developed PCB design tool.
Section 5.1 presents the BDL tool and
describes the features and capabilities: functions, object classes, user
interface it provides. Section 5.3 presents some important issues
within design methodology, focusing on PCB design and generic board design, and
how these are related to flexibility. The notion of a dedicated Board
Description Language (BDL) is presented.
The BDL, which is the programming language used to generate the schematics and
layout for the Barracuda ProtoBoard automatically. It is demonstrated that this
approach is much faster and yields better results than manual Schematic Entry.
The chapter focuses in particular on PCB scripts and provides a comparison of
two PCB design strategies on two forms of design entry. The chapter also covers
potential benefits of PCB scripts and provides practical results demonstrating
these benefits. Worked examples are provided and compared to the results of
manual Schematic Entry. Further, some results of the schematics that were
created using the PCB design tool are described and analyzed. The conclusion
section of the chapter will, among others, compare the experience and results
obtained, with the statements made in the motivation section of
chapter 1.
The last chapter provides a summary of the work performed and reviews the major contributions to the Motorola design process. This chapter points out several areas for future work and discusses implications derived from the current work.