4. Barracuda Prototype Board

4.1 Board Design

The Barracuda PreSilicon Emulation Board is a FLEX10K/E-based prototyping board. It is used for design prototyping of STAR12 Microcontroller. This board is especially suited to perform overall tests on the modules during early stages of their development
The board is equipped with five members (EPF10K30QC240/EPF10K200RC240/EPF10K200QC240) of the ALTERA Flex10kE FPGA family in PQFP240 packages, and system integration components including SRAM, BDM (Background Debug Mode) connector, ALTERA ByteBlaster interface for programming and various connectors for measurement and diagnosis. The ICs are mounted in sockets and can therefore be exchanged easily.

From a testboard we expect accessibility to the required internal and port signals. All user I/O pins (also unused pins) of the FPGA's are routed to Header type connectors. This provides access to all port signals of the Barracuda design as well as to the internal STAR12 MCU bus. Additionally, to visualize the internal IP bus of the interface modules, unused pins of FPGA#3 have been used to route them to connectors. This allows testing the functionality of the MCU except analogue components and to extend the design in future.

Another requirement on the prototype board is a powerful interface to a host computer to easily download test-programs into the on board memory. The Background Debug Mode is used to read and write software into the SRAM without participation of the CPU. So, no loading software has to be developed for the prototype board. During downloading, the processor is halted until program and data have been written completely into memory.

For efficient design analysis, the test system has to be reconfigurable. We used Altera Flex10k FPGA allowing in-circuit reconfigurability for design changes and for customizing any module configuration.

Another demand is extensibility. The board can be mounted with different ALTERA Flex 10K devices in the 240 Pin PQFP package, pin compatible packages have been chosen ranging from a 30.000 gate (EPF10K30QC240) to 200.000 (EPF10K200RC240). This allows for a variety of Microcontroller (Interface) configurations to be tested. Some unused pins of the FPGA are routed each between two device. All unused pins are routed to connectors. In this way additional signals can be visualized or can be connected between devices. We intended to route at least 16 reserved MCU bus signals to each FPGA. This could not be realized because FPGA#1 (CORE) had no reserved pins available.

The Barracuda ProtoBoard includes a configuration header (from an ALTERA ByteBlaster), two configuration RAM (High/Low Byte) that can be used to emulate FLASH memory, RAM and EEPROM, an Oscillator package and some LEDs.
We decided to use FPGA's with PQFP package because mounting of PQFP packages is less a problem than mounting of BGA packages. This is especially true when it comes to pin alignment.

4.2 Features

Supported devices

All FLEX10K /E in 240 or 208-pin PQFP package

Interface Modules
SRAM module

2 SRAM 128kx8, 10 ns access time.

Software

MaxPlus II magnum supports all Altera FPGA/CPLD and all functions.

4.3 Components Description

The Barracuda ProtoBoard is designed for prototyping. Effectively all signals are routed to connectors. Additionally, jumpers wired to all free IO's are provided.

To download programs into the Barracuda ProtoBoard the BDM connector is used.
Assembled programs are directly downloaded to the on board SRAM via the BDM cable. No additional hardware is required.

Table: 4.1 Components Description
Component # Ref. on board Extra information
Parallel transmission connector P1 For parallel communication.
Front side 64-bit connectors CON1, CON2, CON3, CON4 Connector used for data transmission
External power supply print TP3, TP4, TP5, TP6 For stand-alone power supplying. TP4 (2.5V), TP5 (5V), TP6 (GND)
Jumper J1 Jumper field for CORE configuration.
Jumper JMP1, JMP2, JMP3, JMP4, JMP5, JMP6, JMP7, JMP8 Jumper fields for accessing the not used ALTERA FLEX I/Os.
control LEDs DS1 (green),
DS2, DS3, DS4 (red)
Control if the back-end power is OK, 2.5V (DS2), 5V (DS4) and if the ALTERA FLEX configuration is done (DS1).
ALTERA Flex10k200S240 U1 containes modules CPU, FSC, VSC
SRAM Interface (controls FLASH, RAM, EEPROM emulation).
ALTERA Flex10k200S240 U2 containes modules SCI0, SCI1, SPI, I2C, BDLC, PWM, TIMER, CRG, KWU.
ALTERA Flex10k200S240 U3 containes CAN1, CAN2 modules.
ALTERA Flex10k200S240 U4 containes CAN3, CAN4 modules.
ALTERA Flex10k30E208 U5 containes SRAM INT module.
SRAM U10, U11 emulates FLASH, RAM, EEPROM.

4.4 Connector reference
Table: 4.2 Connector Reference
# Ref. on board Description Commercial ref. Prices
TP3, TP4, TP5, TP6 External power supply connector 22-04-1061 $1
P1 ALTERA JTAG connector HE10-10pts (class 2). $2
J1, J2 Jumper fields M2-9971006. $1
U1 ALTERA FPGA #1 EPF10K200SRC240-2. $985
U2 ALTERA FPGA #2 EPF10K130EQC240-1. $670
U3, U4 ALTERA FPGA #3, #4 EPF10K130EQC240-2. $436
U5 ALTERA FPGA #5 EPF10K30EQC208-1. $81
U10, U11 ISSI 1Mbit (128kx8) CMOS asynchronous SRAM IS62C1024. $40
V1, V2, V3, V4 YAMAICHI QFP-Production Use Socket, 240 pin IC149-240-*67-S5. $
V5 YAMAICHI QFP-Production Use Socket, 208 pin IC149-240-*61-S5. $

4.5 Board configuration

Table: 4.3 external power supply connector
PIN # Name Description
1 GND GND plane
2 POS External power supply.
3 VCC Volts plane
4 GND GND plane
5 GND GND plane
6 NEG External power supply.
The J2 external connector provides power supply to:
the 5 volts plane, from an external source, the (NEG1, NEG2) and (POS1, POS2) rails from two external sources.

Table: 4.4 Bit/Byte Blaster Connector
PIN # Name Description
1 DCLK Serial configuration clock
2 GND GND plane
3 CONF_DONE Configuration done
4 VCC Volts plane
5 nCONFIG Configuration Reset & Start
6 NC Not connected
7 nSTATUS Configuration error
8 NC Not connected
9 DATA0 Serial configuration data
10 GND GND plane
The BitBlaster or ByteBlaster connector is dedicated to the FLEX10k device configuration.