Specification of the Parameterizable Fuzzy Controller (PFUZZ) (Version 0.97)

1. Architecture
1.1. Signal Description
Table 1 PFUZZ Signal Description
Pin Direction Bitwidth Description
CLK IN 1 Systemclock.
RESET_N IN 1 Low active reset.
CS_N IN 1 Low active chip select. Low enables PFUZZ to accept data or commands from the CPU during a write cycle, or to transmit data to the CPU during a read cycle.
RW_N IN 1 Low-active read/write. High indicates a read, low a write operation.
ADR IN 3 Addressbus, to select the register to read from or write to.
DIN IN gfdbw CPU data busses use to transfer data and commands between CPU and PFUZZ.
DOUT OUT gfdbw CPU data busses use to transfer data and commands between CPU and PFUZZ.
INT_IN_1 OUT 1 Interrupt when content in DATA_IN register is valid.
INT_IN_0 OUT 1 Interrupt ..
INT_OUT_1 OUT 1 Interrupt when content in DATA_OUT register is valid.
INT_OUT_0 OUT 1 Interrupt ..
ERR OUT 1 Error signal.
DMA_RD_RQ OUT 1 Request to the DMAM to obtain an input DMA service.
DMA_RD_ACK IN 1 Acknowledge for an input DMA service.
DMA_RD_ADR OUT gfabw Input DMA address bus.
DMA_DOUT IN gfdbw Data bus, used to transfer rule base data from the DMA manager DMAM to the PFUZZ.
ANALOG_IN IN gfibw Analog input.
HSIN0 IN 1 Handshake signals for input port.
HSIN1 OUT 1 Handshake signals for input port.
ANALOG_OUT OUT gfobw Analog output.
HSOUT0 IN 1 Handshake signals for output port.
HSOUT1 OUT 1 Handshake signals for output port.
1.2 PFUZZ
Parametrizable Fuzzy Controller

Figure 1. Diagram of the Parameterizable Fuzzy Controller PFUZZ.

1.2 Blockdiagram
Parametrizable Fuzzy Controller

Figure 2. Blockdiagram of the Parameterizable Fuzzy Controller PFUZZ.

1.3 PFUZZ Parameter Description
Table 2 Parameters and their max-, min-, and default values as applicable
VHDL Name Parameter Min Max Default Description
Parameters of Busses
generic_fuzz_ data_bit_width gfdbw 4 256 8 Bitwidth of CPU data bus.
DATA_BUS
generic_fuzz_ internal_bit_width gfibw 4 256 8 Bitwidth of internal data bus.
INTERNAL
generic_fuzz_ digital_input_port gfdip 1 32 8 Number of digital input.
INPUT_PORT
generic_fuzz_ digital_output_port gfdop 1 32 8 Number of digital output.
OUTPUT_PORT
generic_fuzz_ analog_input_port gfaip 1 32 8 Number of analog input.
ANALOG_INPUT
generic_fuzz_ analog_output_port gfaop 1 32 8 Number of analog output.
ANALOG_OUTPUT
Parameters of Control Unit
generic_fuzz_ input_member gfim 1 32 8 Number of membership functions in the input universe of discourse.
INPUT_MEMBER
generic_fuzz_ output_member gfiom 1 32 8 Number of membership functions in output universe of discourse.
OUTPUT_MEMBER
generic_fuzz_member_ precision gfmp 1 256 8 Number of binary vectors characterizing the membership function.
generic_fuzz_member_ bitwidth gfmbw 4 256 16 Number of bits in a single binary vector.
generic_fuzz_rules gfrul 4 256 64 Number of applicable rules.
RULES
generic_fuzz_anteced gfant 1 32 4 Number of antecedents in a rule.
ANTECEDENTS
generic_fuzz_conseq gfcon 1 32 1 Number of consequents in a rule.
CONSEQUENTS
generic_fuzz_ membership_form gfform SINGLETON
S-FORM
Z-FORM
TRIANGLE
TRAPEZODIAL
SINGLETON Form of representation of membership functions.
FORM
generic_fuzz_comput gfcom 1 16 4 Number of fuzzy computational units. FCU
generic_fuzz_data_type gftype INTEGER
FLOAT
INTEGER Data type.
DATA_TYPE
generic_fuzz_error gferr DISABLED
REG
DISABLED Selects error.
ERROR
Parameters of Analog Input Unit
generic_fuzz_ analog_input_unit gfaiu DISABLED
ENABLED
REG DISABLED
REG ENABLED
DISABLED Selects analog input unit.
AN_IN_EN
generic_fuzz_input_ handshake_unit gfihsu DISABLED
ENABLED
REG DISABLED
REG ENABLED
DISABLED Selects output handshake.
HS_IN_EN
generic_fuzz_input_ sampling_unit gfisu DISABLED
REG
DISABLED Enables the input sampling rate to be set via register.
generic_fuzz_input_ sampling_rate gfiisr 10 kHz 100 kHz 15 kHz Input Sampling rate.
INPUT_SAMPLE
Parameters of Analog Output Unit
generic_fuzz_ analog_output_unit gfaou DISABLED
ENABLED
REG DISABLED
REG ENABLED
DISABLED Selects analog output unit.
AN_OUT_EN
generic_fuzz_output_handshake_unit gfohsu DISABLED
ENABLED
REG DISABLED
REG ENABLED
DISABLED Selects output handshake.
HS_OUT_EN
generic_fuzz_output_ sampling_unit gfosu DISABLED
REG
DISABLED Enables the output sampling rate to be set via register.
generic_fuzz_output_ sampling_rate gfosr 10 kHz 100 kHz 15 kHz Input Sampling rate.
OUTPUT_SAMPLE
Parameters of Input Interrupt Unit
generic_fuzz_ input_interrupt_1 gfii1 DISABLED
REG
DISABLED Selects input interrupt 1.
INT_IN_1
generic_fuzz_ input_interrupt_0 gfii0 DISABLED
REG
DISABLED Selects output interrupt 0.
INT_IN_0
Parameters of Output Interrupt Unit
generic_fuzz_ output_interrupt_1 gfoi1 DISABLED
REG
DISABLED Selects output interrupt 1.
INT_OUT_1
generic_fuzz_ output_interrupt_0 gfoi0 DISABLED
REG
DISABLED Selects output interrupt 0.
INT_OUT_0
Parameters of DMA Unit
generic_fuzz_dma_unit gfdu DISABLED
REG
DISABLED Selects DMA unit for data transfer from the rulebase memory.
DMA_EN
generic_fuzz_rule_detect gfrud 0 16 4 Number of rule detection units.
RULE_DETECT
generic_fuzz_ dma_data_order gfddo LITTLE ENDIAN
BIG ENDIAN
REG LITTLE ENDIAN
REG BIG ENDIAN
BIG ENDIAN Sets the DMA data transfer order.
DMA_DDIR
generic_fuzz_ dma_address_direction gfdad INC
DEC
REG INC
REG DEC
REG INC Sets the direction of DMA address count.
DMA_ADIR
Parameters of Inference Unit
generic_fuzz_inference_ min_max gfimm DISABLED
ENABLED
REG
DISABLED Selects inference method
MIN-MAX.
MIN_MAX_EN
generic_fuzz_inference_ product_sum gfips DISABLED
ENABLED
REG
DISABLED Selects inference method
PRODUCT-SUM.
PROD_SUM_EN
generic_fuzz_inference_ tsukamoto gfit DISABLED
ENABLED
REG
DISABLED Selects inference method
TSUKAMOTO.
TSUKAMOTO_EN
generic_fuzz_inference_ takagi_sugeno gfits DISABLED
ENABLED
REG
DISABLED Selects inference method
TAKAGI_SUGENO.
TAK_SUG_EN
Parameters of Defuzzification Unit
Generic_fuzz_defuzz_ maximum gfdm DISABLED
ENABLED
REG
DISABLED Selects defuzzification method
MAXIMUM.
COG_EN
generic_fuzz_defuzz_ centre_of_gravity gfdcog DISABLED
ENABLED
REG
DISABLED Selects defuzzification method
CENTRE_OF_GRAVITY.
COG_EN
generic_fuzz_defuzz_ centre_of_area gfdcoa DISABLED
ENABLED
REG
DISABLED Selects defuzzification method
CENTRE_OF_AREA.
COA_EN
generic_fuzz_defuzz_ height gfdh DISABLED
ENABLED
REG
DISABLED Selects defuzzification method
HEIGHT.
HEIGHT_EN
generic_fuzz_defuzz_centre_of_largest_area gfdcola DISABLED
ENABLED
REG
DISABLED Selects defuzzification method
CENTRE_OF_LARGEST_AREA
COLA_EN
generic_fuzz_defuzz_mean_of_maxima gfmom DISABLED
ENABLED
REG
DISABLED Selects defuzzification method
MEAN_ON_MAXIMA.
MOM_EN
Parameters of Aggregation Unit
generic_fuzz_operator_minimum gfomin DISABLED
REG
DISABLED Selects Aggregation-Operator MINIMUM.
generic_fuzz_operator_ maximum gfomax DISABLED
REG
DISABLED Selects Aggregation-Operator
MAXIMUM.
generic_fuzz_operator_bounded_sum gfobs DISABLED
REG
DISABLED Selects Aggregation-Operator
BOUNDED_SUM.
generic_fuzz_operator_bounded_difference gfobd DISABLED
REG
DISABLED Selects Aggregation-Operator
BOUNDED_DIFFERENCE.
generic_fuzz_operator_bounded_product gfobp DISABLED
REG
DISABLED Selects Aggregation-Operator
BOUNDED_PRODUCT.
generic_fuzz_operator_algebraic_product gfoap DISABLED
REG
DISABLED Selects Aggregation-Operator
ALGEBRAIC_PRODUCT.
2. Register Description
Table 3 Bitallocation of the ENABLE Register
Bit Nr. Name Description Value
7 EN Sets the PFUZZ in operation or power down mode. (pfuzz) 0: PFUZZ off
1: PFUZZ on
6 AN_IN_EN Enables analog input unit.
(gfaiu)
0: DISABLED
1: ENABLED
5 HS_IN_EN Enables input Handshake.
(gfihsu)
0: DISABLED
1: ENABLED
4 ... Reserved for future use. 0
3 ... Reserved for future use. 0
2 AN_OUT_EN Enables analog output unit.
(gfaou)
0: DISABLED
1: ENABLED
1 HS_OUT_EN Enables output Handshake.
(gfohsu)
0: DISABLED
1: ENABLED
0 ... Reserved for future use. 0
Table 4 Bitallocation of the Interrupt Control Register INT CTL
Bit Nr.

Name

Description

Value

7

INT_IN_1_EN Enables input interrupt 1.
(gfii1)
0: DISABLED
1: ENABLED

6

INT_IN_0_EN Enables input interrupt 0.
(gfii0)
0: DISABLED
1: ENABLED

5

INT_OUT_1_EN Enables output interrupt 1.
(gfoi1)
0: DISABLED
1: ENABLED

4

INT_OUT_0_EN Enables output interrupt 0.
(gfoi0)
0: DISABLED
1: ENABLED

3

INT_IN_1 Input interrupt 1.
(gfii1)
0: DISABLED
1: ENABLED

2

INT_IN_0 Input interrupt 0.
(gfii0)
0: DISABLED
1: ENABLED

1

INT_OUT_1 Output interrupt 1.
(gfoi1)
0: DISABLED
1: ENABLED

0

INT_OUT_0 Output interrupt 0.
(gfoi0)
0: DISABLED
1: ENABLED
Table 5 Bitallocation of the DMA Control Register DMA CTL
Bit Nr. Name Description Value

7

... Reserved for future use. 0

6

... Reserved for future use. 0

5

... Reserved for future use. 0

4

... Reserved for future use. 0

3

... Reserved for future use. 0

2

DMA_EN Enables DMA transfer.
(gfdu)
0: DISABLED
1: ENABLED

1

DMA_DDIR Set the direction of the DMA transfer order.
(gfddo)
0: BIG ENDIAN
1: LITTLE ENDIAN

0

DMA_ADIR Sets the direction of the input DMA address count.
(gfad)
0: INCREMENT
1: DECREMENT
Table 6 Bitallocation of the Operation Control Register OPERATION CTL
Bit Nr.

Name

Description

Value

7

6

5

OPERATOR Selects aggregation operator.
(gfomin)
000: MIN
001: MAX
010: BOUNDED_SUM
011: BOUNDED_DIFF
100: BOUNDED_PROD
101: ALGEBRAIC_PROD

4

3

INFERENCE Selects the inference method. 00: MIN_MAX
01: PROD_SUM
10: TSUKAMOTO
11: TAKAGI_SUGENO

2

1

0

DEFUZZ Selects defuzzification method. 000: COG
001: COA
010: HEIGHT
011: COLA
100: MOM
Table 7 Register View
Bit Nr.

DATA TRANSFER

Bit Nr.

ERRORS

7

ENABLE

7

ENABLE

6

PAGE=0

6

PAGE=1

5

EXT IN

5

EXT IN

4

EXT OUT

4

EXT OUT

3

INT CTL

3

INT CTL

2

Reserved for future use.

2

Reserved for future use.

1

VALUE

1

Reserved for future use.

0

RESULT

0

ERR CTL
 

Bit Nr.

DMA TRANSFER

Bit Nr.

OPTIONS

7

ENABLE

7

ENABLE

6

PAGE=2

6

PAGE=3

5

EXT IN

5

EXT IN

4

EXT OUT

4

EXT OUT

3

INT CTL

3

METHOD_CTL

2

DMA CTL

2

OPERATOR_CTL

1

DMA WC

1

INPUT SAMPLE

0

DMA ADR

0

OUTPUT SAMPLE

Copyright © 1998 Andreas Tüchler